(1) Field of the Invention
The present invention relates to a process used to fabricate semiconductor devices, and more specifically to a process used to form salicide, (Self-ALigned metal siLICIDE), layers, only on specific regions of a semiconductor substrate.
(2) Description of the Prior Art
Metal oxide semiconductor field effect transistors, (MOSFET), devices can be fabricated using low resistance, polysilicon word lines, for logic applications, while other applications, such as memory devices, or electro-static discharge, (ESD), protection circuits, are usually fabricated using higher resistance, polysilicon word lines. For cases in which both memory and logic, MOSFET devices, or complimentary metal oxide semiconductor, (CMOS), devices, are used on a single semiconductor chip, low sheet resistance is needed for the polysilicon word line and for the source/drain regions, while higher sheet resistances are needed for the memory components. The use of salicide layers, formed only on the polysilicon and silicon regions, of devices needing lower sheet resistance, has been used to fabricate the higher performing devices, while other regions of the semiconductor chip, not requiring the lower sheet resistance, have been masked from the salicide process, thus resulting in the desired higher sheet resistance components.
The masking of the higher sheet resistance devices, during the process sequence used to form salicide layers on the devices requiring low sheet resistance regions, is usually accomplished using a silicon oxide layer. The metal layer used as a component of the salicide layer, overlying the masking silicon oxide layer, remains unreacted during an anneal cycle that is used to convert the same metal layer to a metal silicide layer, on the exposed polysilicon or silicon regions, of the devices requiring lower sheet resistance. Removal of unreacted metal, from the masking silicon oxide layer, and removal of the masking silicon oxide layer, result in polysilicon and source/drain regions, free of salicide layers, while unmasked counterparts, exhibit the desired, low resistance salicide layers on the polysilicon and source/drain regions, of high performing CMOS logic devices.
Several aspects of the use of silicon oxide layers, in regards to salicide blocking or masking functions, can however result in deleterious structural or device phenomena. First, an anisotropic reactive ion etching, (RIE), procedure used to remove the masking silicon oxide layer, in a first region of the semiconductor substrate, exposing polysilicon and silicon regions to a subsequent salicide layer, can result in the formation of an additional silicon oxide spacer, overlying an existing insulator spacer, located on the sides of the polysilicon word lines, in the first region of the semiconductor substrate. The additional silicon oxide spacer, decreases the design space between polysilicon word lines, and when using designs with sub-micron dimensions, the decreased space can result in the complete blockage of a source/drain region, located between polysilicon word lines, thus not allowing the incorporation of an overlying, low resistance salicide layer. Secondly, the silicon oxide layer, used as a mask for salicide formation, is obtained using low pressure chemical vapor deposition, (LPCVD), or plasma enhanced chemical vapor deposition, (PECVD), procedures, each using tetraethylorthosilicate, (TEOS), as a source. Undensified TEOS oxide layers have a high removal rate in dilute hydrofluoric, (DHF), or buffered hydrofluoric, (BHF), acid solutions. Therefore a BHF or a DHF, pre-clean procedure, performed to remove native oxide from the surface of the polysilicon and silicon regions being readied for salicide formation, results in large, and uncontrollable, thickness decreases, for the TEOS oxide mask that is used to block salicide formation, and therefore may not protect against salicide formation. Densification of the TEOS oxide layer, alleviating the rapid removal rate, during pre-clean procedures, would however adversely influence the thermal budget used for the sub-micron devices.
This invention will describe a composite insulator shape, comprised of a thin silicon nitride layer, overlying a thin TEOS oxide layer, used to block specific regions of a semiconductor substrate, from salicide formation. The composite insulator shape is anisotropically removed from the regions of the semiconductor substrate being readied for salicide formation, however after removal of the masking photoresist shape, which is used to maintain the composite insulator layer in regions not designed for salicide formation, a DHF, BHF, or a wet HF spray is performed to remove the additional TEOS oxide spacer, formed during the anisotropic RIE procedure. The thin nitride layer, of the composite insulator shape, not only remains as a blocking layer during removal of the additional TEOS oxide spacer, but also offers protection from subsequent BHF or DHF, preclean procedures, used prior to metal deposition, or protection from a silicon ion implantation procedure, used for amorphization of source/drain regions, allowing these source/drain regions to remain shallow. Prior art, such as Yoo et al, in U.S. Pat. No. 5,573,980, describe a salicide process, however the use of the novel salicide blocking, composite insulator shape, featured in the present invention, is not described in that prior art.